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3D Integrated Circuits: Materials Challenges 
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Date/Time:
March 25, 2015   12:00pm - 1:30pm
 
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The fabrication of mobile and other electronic devices by three-dimensional integrated circuits (3D ICs) is receiving wide attention. The concept of using 3D ICs to extend the limit of Moore’s Law, by combining chip technology and packaging technology, has been explored for more than 10 years. However, we still do not mass produce 3D IC devices due to low yield and reliability, along with high cost. Most problems are caused by materials selection and integration at the small scale. The presentations in this webinar will cover some of the important aspects of materials challenges in 3D ICs, complementing the articles in the March 2015 issue of MRS Bulletin on this topic.

Three Dimensional Integration-An Overview
Subramanian Iyer, IBM

Cu Pillar Bumping for Advanced Packaging
Eric Perfecto, IBM

Cu Through Silicon Vias for Three Dimensional Integration
Chandrasekara Kothandaraman, IBM
 


 
 
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