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UU4.12 - A Buffer Layer Technique for GaAs Nanowire Growth on Si Substrate 
Date/Time:
April 23, 2014   11:45am - 12:00pm
 
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Gold catalyzed VLS method is widely applied to III-V nanowire (NW) growth directly on Si substrate. However, the easy oxidation of Si and high sensitivity of growth conditions largely limit its controllability. Furthermore, Si dissolves into gold particles at high temperature; it will modify the Au/Si/GaAs interface energy and cause horizontal GaAs NW growth. Gold particles also serve as a Si sink which results in an unintentional doping of NWs. Additionally, TEM reveals there are plenty of stacking faults and twins in the NWs grown under these conditions.To prevent Si contamination, reduce defects in the NW, and improve controllability of GaAs NW growth, we developed a buffer layer technique by introducing a GaAs thin film with predefined polarity before gold dispersion. The surface oxide of buffer layers, GaOx or AsOx, is easily removed during in-situ baking, providing more flexibility on buffer layer treatment time and therefore NW density can be well-controlled by the sitting time of gold colloid on buffer surface, as opposed to the stringent conditions of direct NW growth on Si. The growth temperatures for buffer layer growth were investigated. Generally, NWs grown on buffer layers have high yield of vertical NWs. In addition, a lower buffer growth temperature leads to a smoother buffer morphology and a higher yield of vertical NWs as compared to tilted NWs. As high as ~95.5% of vertical NWs were obtained on buffer layer grown at 400°C. Therefore, a smooth buffer layer provides a good template for vertical NW growth. While high temperature buffer has rough morphology with a lower vertical NW yield of ~86.2%, it results in a perfect crystal quality of NWs with no visible defects and sharp lattice flanges. The lattice distance is measured to be ~3.25Å along growth direction, demonstrating (111) orientation. Obvious defects were observed in samples grown on low temperature buffers, comparatively, indicating NW crystal quality is influenced by buffer crystallinity which is determined by growth temperature. Therefore, a high buffer growth temperature is crucial for high quality NW growth. We need to compromise between vertical NW yield and crystal quality according to specific device application.Usually there are defects in GaAs NW samples regardless of growth methods. The defect-free property we observed here is very promising for GaAs NW based optoelectronic device application. Moreover, the buffer layers effectively eliminate Si contamination by preventing Si diffusion and dissolution, and effectively promote vertical NW growth. The buffer layer technique proposed here could be easily extended to other III-V on Si system for electronic and photonic applications.
 


 
 
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