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BB12.01 - Characterisation of Metal Contact to III-V Materials (Mo/InGaAs) 
April 25, 2014   8:00am - 8:15am

The CMOS device channel material for sub-10nm dimensions has been identified to be major challenge as per the ITRS roadmap. Among the options that are defined by ITRS roadmap is the high mobility III-V based channels. The overall goal of this research is to focus on new III-V materials that are capable of achieving nanometer scale transistors, in support of applications that can operate at 0.3-0.5 V. Our research is focusing on developing the Sb channel based FinFET devices. One of the key challenges is to develop an optimum metal contact to the III-V FinFET channel. In the first phase of this project we are focusing on Molybdenum/InGaAs contacts (moving to InGaSb channels later) to develop basic unit processes and characterization techniques. In this paper we are focusing on the interface characterization between the two layers and presenting our electrical and material assessment. This involves electrical measurements followed by detailed Mo/InGaAs interface studies using SEM and TEM techniques. The characterization process is focused on studying the effect of different fabrication processes and splits on the quality of the Molybdenum/InGaAs interface. To characterize this, Kelvin structures of Molybdenum over InGaAs were fabricated as test structures to measure the sheet resistivity and the contact resistance of the different sample. The starting material bilayer of the samples is InGaAs (150 Ã…) over InP (4000 Ã…), the fabrication sequence involves: the deposition of 30Ã… of Moly over the InGaAs layer, then patterning the Moly to form the nano TLM lines for kelvin test structures. The Moly lines in the test structures are patterned to a minimum contact length of 275nm. Then, an area of the InGaAS layer under the Moly lines is defined as an active layer (Mesa definition), the remaining area is etched by Chlorine based etch chemistry. In a final step, Pad areas are defined using lift-off of Titanium/Gold. In order to study the effect of various fabrication steps, different experimental processes are carried out. This includes the effect of different metal deposition techniques: sputter vs. e-beam evaporation. This is crossed with exposure to plasma damage and the use of “digital etch” to clean the channel to metal interface. The first set of baseline electrical and physical measurements was conducted by our collaborators [1]. Their first set of measurements indicate that the sputtered Mo gives a lower metal sheet resistance, 0.97 Ω/sq and metal to pad contact resistance, 3.7×10-8 Ω.cm2, compared to the evaporated Mo, 5.6 Ω/sq and 4.1×10-8 Ω.cm2, relatively. The samples with the various cleans just finished fabrication and electrical and TEM characterization are under way and will be reported in the meeting.This research is funded by SRC MEESII project P14897.Technical Collaborator: Prof. Jesus del Alamo, EECS, MIT, Boston, USA.[1] A. Guo, “Nano-scale Metal Contacts for Future III-V CMOS,” M.S. thesis, Dept. Electrical Engineering, MIT., 2012

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