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BB5.01 - A Combined Study of the Metal/AlO/InGaAs MOS System Using Capacitance-Voltage Characterization and Hard X-Ray Photoelectron Spectroscopy 
Date/Time:
April 23, 2014   10:00am - 10:15am
 
Speaker:
 
Taxonomy
III-V 
 
 
oxide 
 
 
metal 
 
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One of the major challenges associated with the incorporation of high mobility III-V channel materials into future MOSFETs is the characterization, understanding and passivation of electrically active interface states present at the oxide/III-V interface. Considering the case of the high-/InGaAs MOS system, there is a wide range of interface state concentrations D(E) reported for nominally similar structures [1]. One of the main issues associated with the accurate extraction of D(E) for the high-/InGaAs MOS system is the question of how each gate voltage (V) is related to the corresponding surface Fermi level position (E) relative to the valence band edge (E). For a D(E) which changes density exponentially with E-E, this is clearly a potential source of error and variation between research groups. Moreover, the relationship of E-E to V is further complicated in the case of high D and for MOS systems where the semiconductor has a low conduction band density of states. It has recently been shown that good agreement can be obtained for the E-E at V = 0 V in the SiO/Si [2] and strongly pinned case of the AlO/GaAs MOS systems [3] using a combination of C-V analysis and hard x-ray photoelectron spectroscopy (HAXPES), where the high photon energies used in the synchrotron based HAXPES (2000-5000eV) allow the semiconductor core levels to be detected even in the presence of an overlaying thin metal gate and oxide layer [4].In this work, we report on a combined HAXPES (4150 eV) and C-V study of the surface Fermi level position in the AlO/InGaAs MOS system. Samples with high (Ni) or low (Al) work function metals were employed in an attempt to move the surface Fermi level at V = 0 V. The experimental study included samples for C-V analysis with metal gates (~160 nm) and samples with thinner gates (~5 nm), or no gate, for the comparative HAXPES analysis (HAXPES analysis has no applied gate bias). InGaAs surface Fermi level positions determined by HAXPES revealed surface band bending occurring prior to metal deposition, which is attributed to a combination of fixed oxide charges and donor-type interface states. Following the metal deposition, HAXPES yields very similar surface Fermi level to the results obtained from high frequency C-V analysis at V = 0 V, providing more certainty on D(E) extractions and also bridging the gap between interface chemistry and electrical properties at a buried interface. The InGaAs surface Fermi level does move following metal deposition, but is found to be less than the expected metal-InGaAs work function difference, which is consistent with the partially pinned nature of high-InGaAs interface and suggests a peak interface state density near InGaAs midgap energy.[1] R. Engel-Herbert et al., J. Appl. Phys. 108, 124101 (2010)[2] L. A. Walsh et al., Appl. Phys. Lett.101, 241602 (2012)[3] L. A. Walsh et al., Phys. Rev. B 88, 045322 (2013)[4] K. Kakushima et al., J. Appl. Phys. 104, 104908 (2008)
 


 
 
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