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DD6.07-EE6.07 - Ultimate Scaling Limit of Phase Change Memory: An Ab Initio Study 
April 3, 2013   11:00am - 11:15am

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Al CMP for Low Resistance Gate Fill for 20nm and Beyond Replacement Metal Gate
High Resolution Topography Characterization at Die-Scale of Front End CMP Processes
Reducing Density-induced CMP Non-uniformity for Advanced Semiconductor Technology Nodes
Fluorescence Correlation Spectroscopic Investigation of Surface Adsorption of CMP Slurry Additives on Abrasive Particles
Characterization of Chemically Modified Thin Films for Optimization of Metal CMP Applications